A TI-ADC employs several lower speed sub-ADCs operating in parallel in order to achieve a desired aggregate sampling rate. Thus, each sub-ADC may operate at a lower speed compared to when a single ADC would be used. Differences amongst sub-ADCs (e.g. caused by manufacturing tolerances) result in degraded performance in terms of noise Power Spectral Density (nPSD) and/or Spurious Free Dynamic Range (SFDR). Typical mismatches amongst the sub-ADCs include: DC offset, gain, timing skew/mismatch, frequency response and other nonlinear mismatches. The combined mismatches may be understood as a single time-variant nonlinear system with memory that degrades the performance of the TI-ADC in terms of nPSD and/or SFDR. Calibration is required in order to remove these undesired performance-degrading effects.
Hence, there may be a desire for a calibration architecture.